Low-cost high-efficiency solar module using epitaxial si thin-film absorber and double-sided heterojunction solar cell with integrated module fabrication

ABSTRACT

One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

RELATED APPLICATION

This application is a continuation of, and hereby claims priority under35 U.S.C §120 to, U.S. patent application Ser. No. 12/476,991, AttorneyDocket Number P48-1NUS, entitled “Low-Cost High-Efficiency Solar ModuleUsing Epitaxial Si Thin-Film Absorber and Double-Sided HeterojunctionSolar Cell with Integrated Module Fabrication,” by inventors JiunnBenjamin Heng, Chentao Yu, Zheng Xu, Jianming Fu, and Peijun Ding, filed2 Jun. 2009, which claims the benefit of U.S. Provisional ApplicationNo. 61/183,308, Attorney Docket Number SSP09-1007PSP, entitled “HighEfficiency, Low Cost Photovoltaic Modules Based on Thin EpitaxialSilicon and Substrate Reuse,” by inventors Jiunn Benjamin Heng, ChentaoYu, Zheng Xu, Jianming Fu, and Peijun Ding, filed 2 Jun. 2009, thedisclosures of which are incorporated by reference herein.

BACKGROUND

Field

This disclosure is generally related to solar cells. More specifically,this disclosure is related to a solar cell module based on double-sidedheterojunction solar cells with epitaxial Si thin-film absorber.

Related Art

The negative environmental impact caused by the use of fossil fuels andtheir rising cost have resulted in a dire need for cleaner, cheaperalternative energy sources. Among different forms of alternative energysources, solar power has been favored for its cleanness and wideavailability.

A solar cell converts light into electricity using the photoelectriceffect. There are several basic solar cell structures, including asingle p-n junction, p-i-n/n-i-p, and multi-junction. A typical singlep-n junction structure includes a p-type doped layer and an n-type dopedlayer. Solar cells with a single p-n junction can be homojunction solarcells or heterojunction solar cells. If both the p-doped and n-dopedlayers are made of similar materials (materials with equal band gaps),the solar cell is called a homojunction solar cell. In contrast, aheterojunction solar cell includes at least two layers of materials ofdifferent bandgaps. A p-i-n/n-i-p structure includes a p-type dopedlayer, an n-type doped layer, and an intrinsic (undoped) semiconductorlayer (the i-layer) sandwiched between the p-layer and the n-layer. Amulti-junction structure includes multiple single-junction structures ofdifferent bandgaps stacked on top of one another.

In a solar cell, light is absorbed near the p-n junction generatingcarriers. The carriers diffuse into the p-n junction and are separatedby the built-in electric field, thus producing an electrical currentacross the device and external circuitry. An important metric indetermining a solar cell's quality is its energy-conversion efficiency,which is defined as the ratio between power converted (from absorbedlight to electrical energy) and power collected when the solar cell isconnected to an electrical circuit.

For homojunction solar cells, minority-carrier recombination at the cellsurface due to the existence of dangling bonds can significantly reducethe solar cell efficiency; thus, a good surface passivation process isneeded. In addition, the relatively thick, heavily doped emitter layer,which is formed by dopant diffusion, can drastically reduce theabsorption of short wavelength light. Comparatively, heterojunctionsolar cells, such as Si heterojunction (SHJ) solar cells, areadvantageous. FIG. 1 presents a diagram illustrating an exemplary SHJsolar cell (prior art). SHJ solar cell 100 includes front electrodes102, an n⁺ amorphous-silicon (n⁺ a-Si) emitter layer 104, an intrinsica-Si layer 106, a p-type doped crystalline-Si (c-Si) substrate 108, andan Al backside electrode 110. Arrows in FIG. 1 indicate incidentsunlight. Because there is an inherent bandgap offset between a-Si layer106 and c-Si layer 108, a-Si layer 106 can be used to reduce the surfacerecombination velocity by creating a barrier for minority carriers. Thea-Si layer 106 also passivates the surface of c-Si layer 108 byrepairing the existing Si dangling bonds. Moreover, the thickness of n⁺a-Si emitter layer 104 can be much thinner compared to that of ahomojunction solar cell. Thus, SHJ solar cells can provide a higherefficiency with higher open-circuit voltage (V_(oc)) and largershort-circuit current (J_(sc)).

Fuhs et al. first reported a hetero-structure based on a-Si and c-Sithat generates photocurrent in 1974 (see W. Fuhs et al.,“Heterojunctions of Amorphous Silicon & Silicon Single Crystal,” Int.Conf., Tetrahedrally Bonded Amorphous Semiconductors, Yorktown Hts.,N.Y., (1974), pp. 345-350). U.S. Pat. No. 4,496,788 disclosed aheterojunction type solar cell based on stacked a-Si and c-Si wafers.The so-called HIT (heterojunction with intrinsic thin layer) solar cell,which includes an intrinsic a-Si layer interposed between a-Si and c-Silayers, was disclosed by U.S. Pat. No. 5,213,628. However, all these SHJsolar cells are based on a crystalline-Si substrate whose thickness canbe between 200 μm and 300 μm. Due to the soaring cost of Si material,the existence of such a thick c-Si substrate significantly increases themanufacture cost of existing SHJ solar cells. To solve the problem ofhigh cost incurred by c-Si wafers, a solution is to epitaxially grow ac-Si thin film on a low-cost MG-Si wafer, thus eliminating the need forc-Si wafers. However, such an approach has its own limitations in termsof solar cell efficiency. In a heterojunction solar cell with MG-Sisubstrate, the light passing through the active epitaxial c-Si film willbe subsequently absorbed by the MG-Si substrate, thus limiting theamount of generated J_(sc). In addition, the lack of effectivepassivation between the back surface of the c-Si film and the MG-Sisubstrate limits the V_(oc) as well as J_(sc) due to the significantback surface minority carrier recombination.

One approach to achieve a low-cost and high-efficiency solar cell is totransfer solar cells epitaxially grown on a semiconductor grade c-Siwafer to a low-cost substrate. However, such a process can still consumethe c-Si wafer during the transfer. Moreover, the wafer thickness needsto be more than 500 μm to ensure effective transfer and minimum waferbreakage, making cost an issue.

SUMMARY

One embodiment of the present invention provides a double-sidedheterojunction solar cell module. The solar cell includes a frontsideglass cover, a backside glass cover situated below the frontside glasscover, and a number of solar cells situated between the frontside glasscover and the backside glass cover. Each solar cell includes asemiconductor multilayer structure situated below the frontside glasscover, including: a frontside electrode grid, a first layer of heavilydoped amorphous Si (a-Si) situated below the frontside electrode, alayer of lightly doped crystalline-Si (c-Si) situated below the firstlayer of heavily doped a-Si, and a layer of heavily doped c-Si situatedbelow the lightly doped c-Si layer. The solar cell also includes asecond layer of heavily doped a-Si situated below the multilayerstructure, and a backside electrode situated below the second layer ofheavily doped a-Si.

In a variation on the embodiment, the multilayer structure isepitaxially grown on the surface of a metallurgical-Si (MG-Si)substrate.

In a further variation, the MG-Si substrate further comprises a layer ofporous Si.

In a further variation, the MG-Si substrate is removed prior to theformation of the second layer of heavily doped a-Si using one or more ofthe following techniques: chemical etching, applying a shear orpiezoelectric force, applying a temperature gradient, applying anultra/mega-sonic force, applying a tensile or compressive mechanicalforce, and pumping a pressurized gas into the porous Si layer.

In a variation on the embodiment, at least one side of the lightly dopedc-Si layer is textured.

In a variation on the embodiment, the solar cell module further includesa first adhesive polymer layer situated between the frontside glasscover and the solar cells. The adhesive polymer layer, the frontsideglass cover, and the solar cells are laminated together by applying heatand pressure.

In a further variation, the solar cell module includes a layer offrontside metal wires situated between the frontside electrode grid andthe polymer layer. The frontside metal wires are soldered to thefrontside electrode grid during the lamination process.

In a further variation, the refractive index of the polymer matches theglass's refractive index.

In a variation on the embodiment, the solar cell module includes asecond adhesive polymer layer situated between the backside glass coverand the backside electrode. The backside electrode comprises Ag or Alfinger grid.

In a further variation, the solar cell module includes a layer ofbackside metal wires situated between the backside electrode grid andthe second polymer layer. The backside metal wires are aligned tocorresponding frontside metal wires, thereby forming an electricalconnection between adjacent solar cells.

In a variation on the embodiment, the frontside glass region betweenindividual solar cells is protected by a mask during a subsequentfabrication process.

In a variation on the embodiment, each solar cell further comprises atleast one layer of transparent conductive oxide (TCO) material situatedbetween an electrode and a heavily doped a-Si layer.

In a variation on the embodiment, the lightly doped crystalline-Si layeris deposited using a CVD technique. The thickness of the lightly dopedcrystalline-Si layer is between 5 μm and 100 μm, and the dopingconcentration for the lightly doped crystalline-Si layer is between1×10¹⁶/cm³ and 1×10¹⁷/cm³.

In a variation on the embodiment, at least one heavily doped a-Si layeris deposited using a CVD technique. The thickness of the at least oneheavily doped a-Si layer is between 10 nm and 50 nm, and the dopingconcentration for the at least one heavily doped a-Si layer is between1×10¹⁷/cm³ and 1×10²⁰/cm³.

In a variation on the embodiment, the heavily doped and lightly dopedc-Si layers are n-type doped, wherein the first heavily doped a-Si layeris p-type doped, and wherein the second heavily doped a-Si layer isn-type doped.

In a variation on the embodiment, the heavily doped crystalline-Si layeracts as a back-surface-field (BSF) layer. The heavily dopedcrystalline-Si layer is deposited using a chemical-vapor-deposition(CVD) technique. The thickness of the heavily doped crystalline-Si layeris between 1 μm and 10 μm. The doping concentration for the heavilydoped crystalline-Si layer is between 1×10¹⁷/cm³ and 1×10²⁰/cm³.

In a variation on the embodiment, the solar cell module includes atleast one passivation layer on at least one side of the lightly dopedc-Si layer. The thickness of the passivation layer is between 1 nm and10 nm, and the passivation layer includes at least one of: undoped a-Siand SiO_(x).

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 presents a diagram illustrating an exemplary SHJ solar cell(prior art).

FIG. 2 presents a diagram illustrating the process of fabricating aheterojunction multilayer structure in accordance with an embodiment ofthe present invention. 2A illustrates a MG-Si substrate. 2B illustratesa porous Si bi-layer structure is formed on the surface of MG-Sisubstrate. 2C illustrates a thin layer of heavily doped crystalline-Sithin film grown on top of the porous layer. 2D illustrates a layer oflightly doped crystalline-Si base film grown on top of the heavily dopedcrystalline-Si thin film. 2E illustrates that the surface of the basefilm is textured. 2F illustrates a passivation layer deposited on top ofthe base film. 2G illustrates a heavily doped a-Si emitter layerdeposited on the passivation layer. 2H illustrates a layer oftransparent-conducting-oxide (TCO) deposited on top of the a-Si emitterlayer. 2I illustrates that the edge isolation process is performed toeach individual solar cell. 2J illustrates a frontside electrode gridformed on top of the TCO layer.

FIG. 3 presents a diagram illustrating the process of transferring themultilayer structure to a glass cover in accordance with an embodimentof the present invention. 3A illustrates multiple heterojunctionmultilayer structures arranged in a modular configuration. 3Billustrates a layer of metal wires/mesh laid on top of each multilayerstructure. 3C illustrates an adhesive polymer layer placed on top of allmultilayer structures embedding the metal wires/mesh. 3D illustrates afrontside glass cover/superstrate placed on top of adhesive polymerlayer. 3E illustrates the side view of a solar cell module after thelamination of a front cover glass. 3F illustrates a vacuum chuck appliedto frontside glass cover and a vacuum chuck applied to the backside ofeach multilayer structure.

FIG. 4 presents a diagram illustrating the process of fabricatingbackside heterojunctions in accordance with an embodiment of the presentinvention. 4A shows the flipped solar module. 4B illustrates that thebackside of the solar cell is textured. 4C illustrates a protective“mask” applied to the solar cell module. 4D illustrates an ultra-thinbackside passivation layer deposited on the textured back surface of thesolar cell. 4E illustrates a heavily doped a-Si layer deposited on topof backside passivation layer. 4F illustrates a TCO layer deposited onthe heavily doped a-Si layer. 4G illustrates a backside electrode formedon top of the TCO layer. 4H illustrates the removal of the protectivemask.

FIG. 5 presents a diagram illustrating a process of applying a backsideprotective cover to the solar cell module in accordance with anembodiment of the present invention. 5A illustrates a partially finishedsolar cell module. 5B illustrates a layer of metal wires/mesh pre-laidon the backside of each individual solar cell. 5C illustrates a layer ofadhesive polymer placed on the backside of module. 5D illustrates alayer of protective backside cover placed on top of polymer layer. 5Eillustrates the side view of a completed solar cell module.

FIG. 6 presents a diagram illustrating a process of fabricating adouble-sided heterojunction single wafer solar cell in accordance withan embodiment of the present invention. 6A illustrates a layer of metalwires/mesh pre-laid on top of a single-wafer frontside heterojunctionmultilayer structure. 6B illustrates that the multilayer structure isattached to a layer of adhesive polymer. 6C illustrates vacuum chucksattached to the polymer layer and the MG-Si substrate. 6D illustratesthe back side structures of the single wafer solar cell. 6E illustratesthe partial removal of the front side polymer layer. 6F illustrates thatthe selected individual solar cells are arranged in a modularconfiguration. 6G illustrates the lamination of a frontside glasssuperstrate and a backside protective cover. 6H illustrates the framedsolar module.

In the figures, like reference numerals refer to the same figureelements.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled inthe art to make and use the embodiments, and is provided in the contextof a particular application and its requirements. Various modificationsto the disclosed embodiments will be readily apparent to those skilledin the art, and the general principles defined herein may be applied toother embodiments and applications without departing from the spirit andscope of the present disclosure. Thus, the present invention is notlimited to the embodiments shown, but is to be accorded the widest scopeconsistent with the principles and features disclosed herein.

Overview

Embodiments of the present invention provide a “double-sided”heterojunction solar cell module. To fabricate a double-sidedheterojunction solar cell, a multilayer heterojunction structure isfirst grown on top of an MG-Si substrate. The multilayer structureincludes a thin layer of heavily doped c-Si acting as aback-surface-field (BSF) layer, a layer of lightly doped c-Si on top ofthe heavily doped c-Si layer as a base layer, a thin layer of intrinsica-Si acting as a passivation layer, and a layer of heavily doped a-Si asan emitter. In addition, the multilayer structure includes a layer oftransparent-conducting-oxide (TCO) and a frontside electrode grid. Inorder to be able to passivate the backside of the base film, someembodiments transfer the multilayer structure to a glass cover andsubsequently remove the MG-Si substrate. Some embodiments implement alow-cost modular process in which a number of fabricated multilayerstructures are laminated to a glass cover with the assistance of anadhesive polymer layer. The removed substrate can be recycled for futurefabrication. After the removal of the MG-Si substrates, a thin layer ofintrinsic a-Si and a thin layer of heavily doped a-Si are deposited onthe backside of the base films to effectively passivate the backside ofthe base films. Subsequently, a layer of TCO and a backside electrodeare deposited, and a backside glass cover is laminated to finish themodule fabrication. To provide electrical connection to and from a solarcell, Cu wires are pre-laid between the glass covers and the electrodes,and the soldering of the Cu wires to the electrodes is performedconcurrently with the lamination process.

Heterojunction Multilayer Structure

Before being transferred to a frontside glass cover, which acts as asupporting structure for subsequent fabrication processes, aheterojunction multilayer structure is first formed on a low-cost MG-Sisubstrate. FIG. 2 presents a diagram illustrating the process offabricating a heterojunction multilayer structure in accordance with anembodiment of the present invention.

In operation 2A, an MG-Si substrate 200 is prepared. Because MG-Si ismuch cheaper than solar grade or semiconductor grade c-Si, solar cellsbased on MG-Si substrates have a significantly lower manufacture cost.The purity of MG-Si is usually between 98% and 99.99%. To ensure highefficiency of the subsequently fabricated solar cell, the starting MG-Sisubstrate ideally has a purity of 99.9% or better. Prior to anyfabrication processes, a low-cost MG-Si wafer (with resistivity between0.001 Ohm-cm and 0.1 Ohm-cm) undergoes an acidic chemical polish toremove any surface defects and to produce a smooth surface. In oneembodiment, the acidic chemical polish process uses HF, HNO₃, and otheradditives.

In operation 2B, a porous Si bi-layer structure is formed on the surfaceof MG-Si substrate 200. Porous Si bi-layer structure 202 includes alow-porosity Si layer 204 and a high-porosity Si layer 206. In someembodiments, layer 204 has a porosity level between 15% and 30% and athickness between 0.8 μm and 1.5 μm. In some embodiments, layer 206 hasa porosity level between 50% and 70% and a thickness between 0.1 μm and0.3 μm. To construct bi-layer structure 202, some embodiments etch thesurface of the MG-Si wafer using an electrochemical etching techniquewhich applies HF solution and a current. The desired Si porosity leveland porous layer thickness can be achieved by controlling the currentdensity. The combination of a layer with high porosity and a layer withlow porosity ensures not only an easier separation of the substrate(requires high porosity beneath the surface) but also a high-qualityepitaxial film growth (requires low porosity at the surface). Someembodiments form multiple porous Si layers on the surface of MG-Sisubstrate 200.

Operation 2B also includes a process that can further purify the surfaceof the MG-Si wafer to ensure the quality of the subsequent epitaxialgrowth. In one embodiment, MG-Si substrate 200 is baked at a temperaturebetween 1100° C. and 1250° C. in a chemical-vapor-deposition (CVD)chamber filled with hydrogen (H₂) in order to remove nativesilicon-oxide in the substrate. Afterwards, at approximately the sametemperature, hydrogen chloride (HCl) gas is introduced inside the CVDchamber to leach out any residual metal impurities from MG-Si substrate200, thus further preventing the impurities from diffusing into thesubsequently grown c-Si thin films. Due to the fact that metalimpurities, such as iron, have a high diffusion coefficient at thistemperature, the metal impurities tend to migrate to the surface ofsubstrate 200, and react with the HCl gas to form volatile chloridecompounds. The volatile chloride compounds can be effectively purgedfrom the chamber using a purge gas, such as H₂. Note that themetal-impurity leaching process can be carried out either in the CVDchamber, which is subsequently used for the growth of crystalline-Sithin films, or in another stand-alone furnace. The metal-impurityleaching process can take between 1 minute and 120 minutes. MG-Sisubstrate 200 can be either p-type doped or n-type doped. In oneembodiment, MG-Si substrate is n-type doped. Also note that in additionto an MG-Si substrate, it is also possible to use a more expensiveFloatzone, Caochralski, or solar grade wafer as a growth substrate.

In operation 2C, a thin layer of heavily doped (doping concentrationgreater than 1×10¹⁷/cm³) c-Si thin film 210 is epitaxially grown on thesurface of low-porosity Si layer 204. Various methods can be used toepitaxially grow c-Si thin film 210 on MG-Si substrate 200. In oneembodiment, c-Si thin film 210 is grown using a thermal CVD process.Various types of Si compounds, such as SiH₄, SiH₂Cl₂, and SiHC₃, can beused as a precursor in the CVD process to form c-Si thin film 210. Inone embodiment, SiHC₃ (TCS) is used due to its abundance and low cost.C-Si thin film 210 can be either p-type doped or n-type doped. In oneembodiment, c-Si thin film 210 is n-type doped. The doping concentrationof thin film 210 can be between 1×10¹⁷/cm³ and 1×10²⁰/cm³, and thethickness of thin film 202 can be between 1 μm and 10 μm. The dopinglevel should not exceed a maximum limit, which may cause misfitdislocations in the film. C-Si thin film 210 is heavily doped to act asback-surface field (BSF), impurity barrier, and contaminant getter layerfor reducing electron-hole recombination at the surface of thesubsequently grown base film.

In operation 2D, a layer of lightly doped (doping concentration lessthan 1×10¹⁷/cm³) c-Si base film 212 is epitaxially grown on top of thinfilm 210. The growth process of base film 212 can be similar to thatused for thin film 210. Similarly, base film 212 can be either p-typedoped or n-type doped. In one embodiment, base film 212 is lightly dopedwith an n-type dopant, such as phosphorus. The doping concentration ofbase film 212 can be between 1×10¹⁶/cm³ and 1×10¹⁷/cm³, and thethickness of base film 212 can be between 5 μm and 100 μm. After filmdeposition, in operation 2E, the surface of base film 212 is textured tomaximize light absorption inside the solar cell, thus further enhancingefficiency. The surface texturing can be performed using various etchingtechniques including dry plasma etching and wet chemical etching. Theetchants used in the dry plasma etching include, but are not limited to:SF₆, F₂, and NF₃. The wet chemical etchant can be an alkaline solution.The shapes of the surface texture can be pyramids or inverted pyramids,which are randomly or regularly distributed on the surface of base film212.

In operation 2F, a passivation layer 214 is deposited on top of basefilm 212. Passivation layer 214 can significantly reduce the density ofsurface minority-carrier recombination via hydrogenation passivation ofsurface defect states, as well as by the built-in heterojunction bandgapoffset, hence resulting in higher solar cell efficiency. Passivationlayer 214 can be formed using different materials such as intrinsic a-Sior silicon-oxide (SiO_(x)). Techniques used for forming passivationlayer 214 include, but are not limited to: PECVD, sputtering, andelectron beam (e-beam) evaporation. The thickness of passivation layer214 can be between 2 nm and 10 nm. Note that such thickness is thinenough to allow tunneling of majority carriers, thus ensuring low seriesresistance of the solar cell. In some embodiments, a mixture of SiH₄ andH₂ gases is injected into a PECVD chamber at a pressure of 250-750mTorr, an RF power of 20-75 mW/cm², and a temperature of 100-200° C. inorder to form passivation layer 214 that includes intrinsic a-Si.

In operation 2G, a heavily doped a-Si layer is deposited on passivationlayer 214 to form an emitter layer 216. Depending on the doping type ofbase film 212, emitter layer 216 can be either n-type doped or p-typedoped. In one embodiment, emitter layer 216 is heavily doped with ap-type dopant. The doping concentration of emitter layer 216 can bebetween 1×10¹⁷/cm³ and 1×10²⁰/cm³. The thickness of emitter layer 216can be between 10 nm and 50 nm. Techniques used for depositing emitterlayer 216 include PECVD. Some embodiments form emitter layer 216 byinjecting a mixture of B₂H₆ (or PH₃), SiH₄ and H₂ gases into a PECVDchamber operating at a pressure of 250-750 mTorr, an RF power of 20-75mW/cm², and a temperature of 125-250° C. The ultra-thin a-Si layerstack, which includes passivation (intrinsic a-Si) layer 214 and heavilydoped a-Si layer 216, can improve the absorption efficiency of shortwavelength incident light of the solar cell, thus leading to higherefficiency.

In operation 2H, a layer of transparent-conducting-oxide (TCO) isdeposited on top of emitter layer 216 to form a conductiveanti-reflection layer 218. Examples of TCO include, but are not limitedto: indium-tin-oxide (ITO), tin-oxide (SnO_(x)), aluminum dopedzinc-oxide (ZnO:Al), or Ga doped zinc-oxide (ZnO:Ga). Techniques usedfor forming anti-reflection layer 218 include, but are not limited to:PECVD, sputtering, and e-beam evaporation.

In operation 2I, an edge isolation process is performed to eachindividual solar cell to ensure electrical insulation between emitterlayer 216 and base film 212. The edge isolation can be done using atleast one of the following techniques: chemical wet etching, plasma dryetching, and laser scribing.

In operation 2J, frontside electrode grid 220 is formed on top ofanti-reflection layer 218. Frontside electrode grid 220 can be formedusing various metal deposition techniques including, but not limited to:screen printing of Ag paste, aerosol printing of Ag ink, and e-beamevaporation. The formation of frontside electrode grid completes thefabrication of a multilayer structure with front heterojunction. It isimportant to ensure that an ohmic contact is formed between frontsideelectrode grid 220 and anti-reflection layer 218 by using a suitablework function. In some embodiments, a sorting process is performed afterthe completion of the heterojunction multilayer structure.

Layer Transfer

In order to passivate the backside of base film 212, some embodiments ofthe present invention remove the MG-Si substrate and transfer thepreviously completed heterojunction multilayer structure to a glasscover. FIG. 3 presents a diagram illustrating the process oftransferring the multilayer structure to a glass cover in accordancewith an embodiment of the present invention.

In operation 3A, multiple previously fabricated heterojunctionmultilayer structures, including structure 302, are arranged in amodular configuration 300. Various modular configurations can beapplied. For example, module configuration 300 shown in FIG. 3Ademonstrates a 6-cell configuration. Other configurations includingdifferent numbers of cells, such as 36, 72, and 96 cells, and differentgeometric configurations, such as a regular matrix formation orirregular formations, are also possible. Note that each individualstructure can be hold in place by a vacuum chuck with frontsideelectrode grid 304 facing up. FIG. 3A demonstrates the top view ofmodular configuration 300.

In operation 3B, a layer of metal wires/mesh is laid on top of eachmultilayer structure to provide electrical connection to the frontsideof the multilayer structure. For example, metal wires/mesh 306 is placedin such a way that the wires run vertically across frontside electrodegrid 304. In one embodiment, metal wires 306 include tin-lead-silvercoated Cu wires.

In operation 3C, an adhesive polymer layer 308 is placed on top of allmultilayer structures embedding the metal wires/mesh. To ensureexcellent light transmission, the refractive index of adhesive polymerlayer 308 matches that of a subsequently applied frontside glass cover.Examples of index-matching polymer include, but are not limited to:ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, andthermal plastic.

In operation 3D, a frontside glass cover/superstrate 310 is placed ontop of adhesive polymer layer 308, and heat and pressure are applied tocure polymer layer 308. As the result of the curing, the multilayerstructures are laminated on polymer layer 308, and polymer layer 308 islaminated on frontside glass cover 310. In addition, during thelamination process, metal wires/mesh 306 is soldered to correspondingfrontside electrode grid 304, thus forming corresponding bus bars. Notethat the one-step lamination and soldering process is a cost-effectiveway to realize electrical connection and the frontside protection of thesolar cell module. In some embodiments, the temperature for curingpolymer layer 308 is between 150° C. and 180° C.

FIG. 3E illustrates the side view of a solar cell module after thelamination of a front cover glass in accordance with an embodiment ofthe present invention. Note that the sequence of operations forachieving the configuration shown in FIG. 3E can be different than thesequence shown in FIGS. 3A-3D. In some embodiments, polymer layer 308and metal wires/mesh 306 are laid on the surface of frontside glasscover 310 sequentially, and the multilayer structures are flipped upsidedown to be placed on corresponding metal wires/mesh 306.

Once the frontside of multilayer structures 302 is protected, it ispossible to perform layer transferring, during which MG-Si substrate 200is removed. In operation 3F, a vacuum chuck 312 with uniform vacuum isapplied to frontside glass cover 310 and a vacuum chuck 314 is appliedto the backside of each multilayer structure in order to remove MG-Sisubstrate 200 via mechanical forces. Due to the existence of highporosity Si layer 206, which forms a line of weakness, MG-Si substrate200 can be separated from the rest of the multilayer structure 302.Various techniques can be used to separate MG-Si substrate 200 fromstructure 302, including but not limited to: chemical wet etching,applying shear or piezoelectric forces, applying a temperature gradient,applying ultra/mega-sonic resonance force, applying tensile orcompressive mechanical forces, and pumping a pressurized gas (such asH₂) into the porous Si region. Note that the detachment of MG-Sisubstrate 200 can be separately performed for each individual multilayerstructure, or in a batch for the whole module. Detached MG-Si substrate200 can be subsequently recycled and reused as a substrate for a newepitaxial growth, thus significantly reducing the cost of the solar cellfabrication process. Some embodiments use various etching methods, suchas chemical wet etching, plasma dry etching, and chemical mechanicalpolishing, to etch off MG-Si substrate 200. In these scenarios, the costsavings of recycling/reusing MG-Si substrate 200 are forfeited.

Backside Passivation

After the detachment/removal of MG-Si substrates, the backside of thec-Si base films becomes accessible for passivation. FIG. 4 presents adiagram illustrating the process of fabricating backside heterojunctionsin accordance with an embodiment of the present invention.

In operation 4A, the solar cell module is flipped over and the residualporous Si layer is removed to expose the backside of epitaxial c-Sifilms including BSF layer 210. For better demonstration, FIG. 4A onlyshows the cross section of one solar cell. It is advantageous to removethe residual porous Si layer because its high-density defects sites canresult in increased minority carrier recombination at the back surfaceof the solar cell, thus reducing cell efficiency. Various etchingtechniques, such as chemical wet etching, can be used to remove theresidual porous Si layer.

In operation 4B, the backside of the solar cell is textured using eitherchemical wet etching or plasma dry etching techniques. The texturing cansignificantly improve the amount of light absorbed by c-Si films,including BSF layer 210 and base film 212.

Operation 4C is an optional operation, during which a protective “mask”402 is applied to the solar cell module. Mask 402 covers the entiresolar cell module, including the polymer/glass regions between solarcells, except for the backside of individual solar cells. Protectivemask 402 can be formed by a Tyflon® release paper which can subsequentlybe easily peeled off, or by a loading and unloading panel cartridge withcutouts.

In operation 4D, an ultra-thin backside passivation layer 404 isdeposited. The material and techniques used to perform operation 4D aresimilar to those of operation 2F. For example, passivation layer 404 caninclude intrinsic a-Si or SiO_(x). The thickness of backside passivationlayer 404 can be between 2 nm and 10 nm.

In operation 4E, a heavily doped a-Si layer 406 is deposited on top ofbackside passivation layer 404. The deposition process of a-Si layer 406is similar to that of operation 2G. Depending on the doping type of basefilm 212, heavily doped a-Si layer 406 can be n-type doped or p-typedoped. In one embodiment, heavily doped a-Si layer 406 is n-type doped.The formation of a heterojunction between the a-Si layers (layers 404and 406) and base film 212 creates a potential barrier for minoritycarriers at the backside of base film 212, thus effectively decreasingminority carrier recombination at the back surface. Consequently, highersolar cell efficiency (greater than 19.5%) can be achieved. In someembodiments, operations 4D and 4E are skipped, resulting in asingle-sided heterojunction solar cell, which may have lower cellefficiency. However, by skipping the deposition of the a-Si stack(layers 404 and 406), the solar cell module can avoid the hightemperature and high pressure PECVD process, thus preserving theintegrity of frontside adhesive polymer layer 308.

In operation 4F, a TCO layer 408 is deposited to make both ananti-reflection layer and a conductive layer. The process of forming TCOlayer 408 is similar to operation 2H.

In operation 4G, a backside electrode 410 is formed on top of TCO layer408. In some embodiments, backside electrode 410 can be in a gridpattern instead of covering the whole backside. Techniques fordepositing backside electrode 410 can include Ag or Al screen printingand metal evaporation.

In operation 4H, protective mask 402 is removed. Note that in caseswhere no protective mask is applied, an edge isolation operation, suchas laser isolation, will be performed after operation 4F to eliminatepossible short circuits among the cells.

Backside Glass Cover

After the fabrication of the backside heterojunction, a protectivebackside glass/polymer cover is applied to the backside of the solarcell module. The process of applying the backside glass/polymer cover issimilar to that of the frontside glass cover. FIG. 5 presents a diagramillustrating a process of applying a backside protective cover to thesolar cell module in accordance with an embodiment of the presentinvention.

In operation 5A, a partially finished solar cell module 500 is placedwith the backside of solar cells, such as solar cell 502 and solar cell504, facing upward, whereas glass cover/superstrate 506 is facingdownward.

In operation 5B, a layer of metal wires/mesh is pre-laid on the backsideof each individual solar cell. For example, metal wire/mesh 508 isplaced on the backside of solar cell 502, thus providing electricalaccess to the backside electrode of cell 502. In some embodiments, metalwires 508 include tin-lead-silver coated Cu wires. Note that allbackside metal wires/meshes are placed in such a way that they arealigned to corresponding frontside metal wires/meshes to form a seriesof interconnected solar cells as required in a solar cell modulearrangement. For example, metal mesh 508 is placed so that its soldertab 510 is directly contacting the solder tab of the frontside metalmesh of solar cell 504, thus forming a series connection between solarcell 502 and solar cell 504.

In operation 5C, a layer of adhesive polymer 512 is placed on thebackside of module 500. Ideally, adhesive polymer layer 512 has a lowrefractive index and an excellent light transmission coefficient.Materials that can be used to form adhesive polymer layer 512 include,but are not limited to: ethylene-vinyl acetate (EVA), acrylic,polycarbonate, polyolefin, and thermal plastic.

In operation 5D, a layer of protective backside cover 514 is placed ontop of polymer layer 512, and heat and pressure are applied toconcurrently cure polymer layer 512 and solder backside metal wires/meshto the backside electrodes. Backside cover 514 can be formed using glassor a polymer, such as Tedlar®. The curing of polymer layer 512 resultsin the lamination of backside cover 514 to solar cell module 500. Inaddition, the lamination process involves adhesion and vacuum sealingbetween frontside polymer layer 308 and backside polymer layer 512. As aresult, solar cell module 500 is sealed between the frontside glasssuperstrate and the backside cover, thus preventing damages caused byexposure to environmental factors. Subsequently, a standardframing/trimming process and formation of a junction box are performedto finish the manufacture of solar cell module 500. In the end, thecompleted solar cell module is tested. FIG. 5E illustrates the side viewof a completed solar cell module in accordance with an embodiment of thepresent invention.

Single Wafer Process

In some embodiments, instead of using a modular process to fabricate thebackside heterojunctions, a single wafer process is applied to fabricateindividual solar cells before putting them into a module. FIG. 6presents a diagram illustrating a process of fabricating a double-sidedheterojunction single wafer solar cell in accordance with an embodimentof the present invention.

In operation 6A, a layer of metal wires/mesh 606 is pre-laid on top of apreviously fabricated (after the completion of operation 2J)single-wafer frontside heterojunction multilayer structure 602, which isplaced with its frontside electrode grid 604 facing upward.

In operation 6B, multilayer structure 602 is attached to a layer ofadhesive polymer 608 via a lamination process. During the laminationprocess, metal wires/mesh 606 is soldered to frontside electrode 604.

In operation 6C, vacuum chucks are attached to polymer layer 608 andMG-Si substrate 612 to separate the MG-Si substrate from the epitaxialc-Si films. Techniques that can be used to separate MG-Si substrate 612are similar to the ones used in operation 3F.

In operation 6D, the single wafer solar cell undergoes backsideprocessing similar to the ones in operations 4A-4H to accomplishbackside texturing, depositing a passivation layer 614, depositing aheavily doped a-Si layer 616, depositing a TCO layer 618, and depositinga backside electrode grid 620.

In operation 6E, the frontside polymer layer 608 is partially removed toexpose the frontside metal wires/mesh 606, thus enabling cell leveltesting and sorting.

In operation 6F, the selected individual solar cells are arranged in amodular configuration before applying a frontside polymer layer 622, abackside metal wires/mesh 624, and a backside polymer layer 626. Notethat backside metal wires/mesh 624 is aligned to corresponding frontsidemetal wires/mesh in order to form a series of interconnected solarcells.

In operation 6G, a frontside glass superstrate 628 and a backsideprotective cover 630, which can be made of glass or Tedlar®, arelaminated to the solar cell module via curing of polymer layers 622 and626. Similarly, backside metal wires/mesh 624 is soldered to backsideelectrode grid 620 during the lamination process.

In operation 6H, a standard framing/trimming process and the formationof a junction box are performed to finish the manufacture of solar cellmodule 600.

The foregoing descriptions of various embodiments have been presentedonly for purposes of illustration and description. They are not intendedto be exhaustive or to limit the present invention to the formsdisclosed. Accordingly, many modifications and variations will beapparent to practitioners skilled in the art. Additionally, the abovedisclosure is not intended to limit the present invention.

What is claimed is:
 1. A solar module, comprising: a first photovoltaicstructure; a second photovoltaic structure positioned adjacent to thefirst photovoltaic structure, wherein each of the first and secondphotovoltaic structures comprises a first electrode positioned on afirst surface and a second electrode positioned on an opposite surface;and wherein a solder tab of the first electrode of the firstphotovoltaic structure is in direct contact with a solder tab of thesecond electrode of the second photovoltaic structure, thereby enablinga serial connection between the first and second photovoltaicstructures.
 2. The solar module of claim 1, further comprising: a firstcover; and a second cover.
 3. The solar module of claim 2, furthercomprising: a first adhesive polymer layer positioned between the firstcover and the photovoltaic structures; and a second adhesive polymerlayer positioned between the second cover and the photovoltaicstructures; wherein the first and second adhesive polymer layers, thefirst and second covers, and the first and second photovoltaicstructures are laminated together.
 4. The solar module of claim 3,wherein the first cover comprises glass, and wherein a refractive indexof the first adhesive polymer layer matches a refractive index of theglass.
 5. The solar module of claim 4, wherein the first adhesivepolymer layer comprises one or more selected from a group consisting of:ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, andthermal plastic.
 6. The solar module of claim 1, wherein each of thefirst and second photovoltaic structures comprises: a lightly dopedcrystalline-Si layer positioned between the first and second electrodes;a first heavily doped amorphous Si layer positioned between the firstelectrode and the lightly doped crystalline-Si layer; and a secondheavily doped amorphous Si layer positioned between the second electrodeand the lightly doped crystalline-Si layer, wherein the first and secondheavily doped amorphous Si layers have opposite conductive doping types.7. The solar module of claim 6, wherein each of the first and secondphotovoltaic structures further comprises at least one transparentconductive oxide layer positioned between an electrode and a heavilydoped amorphous Si layer.
 8. The solar module of claim 6, wherein thelightly doped crystalline-Si layer is formed using a chemical vapordeposition technique, wherein a thickness of the lightly dopedcrystalline-Si layer is between 5 μm and 100 μm, and wherein a dopingconcentration for the lightly doped c-Si layer is between 1×10¹⁶/cm³ and1×10¹⁷/cm³.
 9. The solar module of claim 6, wherein at least one heavilydoped crystalline-Si layer is formed using a chemical vapor depositiontechnique, wherein a thickness of the at least one heavily dopedcrystalline-Si layer is between 10 nm and 50 nm, and wherein a dopingconcentration of the at least one heavily doped a-Si layer is between1×10¹⁷/cm³ and 1×10²⁰/cm³.
 10. The solar module of claim 6, wherein eachof the first and second photovoltaic structures further comprises apassivation layer on at least one surface of the lightly dopedcrystalline-Si layer, wherein a thickness of the passivation layer isbetween 1 nm and 10 nm, and wherein the passivation layer includes atleast one of: undoped a-Si and SiO_(x).
 11. The solar module of claim 1,wherein the first or second electrode comprises: Cu or tin-lead-silvercoated Cu.
 12. A solar panel, comprising: a first cover; a second cover;and a plurality of photovoltaic structures positioned between the firstand second covers, wherein a respective photovoltaic structure comprisesa first electrode positioned on a first surface and a second electrodepositioned on an opposite surface of the photovoltaic structure; andwherein the plurality of photovoltaic structures are arranged in a waythat a solder tab of the first electrode of a first photovoltaicstructure is in direct contact with a solder tab of the second electrodeof an adjacent photovoltaic structure, thereby enabling a serialconnection between the first photovoltaic structure and the adjacentphotovoltaic structure.
 13. The solar panel of claim 12, furthercomprising: a first adhesive polymer layer positioned between the firstcover and the plurality of photovoltaic structures; and a secondadhesive polymer layer positioned between the second cover and theplurality of photovoltaic structures; wherein the first and secondadhesive polymer layers, the first and second covers, and the pluralityof photovoltaic structures are laminated together.
 14. The solar panelof claim 13, wherein the first or second adhesive polymer layercomprises one or more selected from a group consisting of:ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, andthermal plastic.
 15. The solar panel of claim 13, wherein thephotovoltaic structure comprises: a lightly doped crystalline-Si layerpositioned between the first and second electrodes; a first heavilydoped amorphous Si layer positioned between the first electrode and thelightly doped crystalline-Si layer; and a second heavily doped amorphousSi layer positioned between the second electrode and the lightly dopedcrystalline-Si layer, wherein the first and second heavily dopedamorphous Si layers have opposite conductive doping types.
 16. The solarpanel of claim 15, wherein the photovoltaic structure further comprisesat least one transparent conductive oxide layer positioned between anelectrode and a heavily doped amorphous Si layer.
 17. The solar panel ofclaim 15, wherein the lightly doped crystalline-Si layer is formed usinga chemical vapor deposition technique, wherein a thickness of thelightly doped crystalline-Si layer is between 5 μm and 100 μm, andwherein a doping concentration for the lightly doped c-Si layer isbetween 1×10¹⁶/cm³ and 1×10¹⁷/cm³.
 18. The solar panel of claim 15,wherein at least one heavily doped crystalline-Si layer is formed usinga chemical vapor deposition technique, wherein a thickness of the atleast one heavily doped crystalline-Si layer is between 10 nm and 50 nm,and wherein a doping concentration of the at least one heavily dopeda-Si layer is between 1×10¹⁷/cm³ and 1×10²⁰/cm³.
 19. The solar panel ofclaim 15, wherein the photovoltaic structure further comprises apassivation layer on at least one surface of the lightly dopedcrystalline-Si layer, wherein a thickness of the passivation layer isbetween 1 nm and 10 nm, and wherein the passivation layer includes atleast one of: undoped a-Si and SiO_(x).
 20. The solar panel of claim 12,wherein the first or second electrode comprises: Cu or tin-lead-silvercoated Cu.